1. Field of the Invention
The present invention relates to a data reading technique of a semiconductor storage apparatus, particularly to a fast data reading technique.
2. Description of the Related Art
When a semiconductor storage apparatus (e.g., NOR type flash memory) is accessed at random, a series of reading operation including: selecting a cell for each address input; sensing cell data; and outputting the data is repeated. Therefore, a certain given time is required, and the data cannot be outputted faster.
On the other hand, a serial access operation includes: selecting cells corresponding to a plurality of addresses present on the same word line at the same time; sensing the data; latching the sensed data; and sequential outputting the latched data in synchronization with a clock from the outside. Therefore, a fast data reading is apparently realized.
Furthermore, when the latched data is sequential outputted, a next group of cells are sensed in a chip. Since a so-called xe2x80x9cpipeline readingxe2x80x9d is performed, an internal reading delay can be eliminated in and after a first access, and the fast data reading is enabled.
The xe2x80x9cpipeline readingxe2x80x9d has heretofore been realized by dividing a memory cell array into two, and disposing a decoder and sense amplifier in the two arrays, respectively. Therefore, a chip area has largely increased.
A semiconductor device according to an aspect of the invention comprises: first to eighth bit lines; a plurality of memory cells being connected to the first to eighth bit lines; first to eighth column selection transistors, one of a source and drain of each of the first to eighth column selection transistors being connected to a corresponding one of the first to eighth bit lines; ninth to twelfth column selection transistors, one of a source and drain of the ninth column selection transistor being connected to the other of the source and drain of each of the first and second column selection transistors, one of a source and drain of the tenth column selection transistor being connected to the other of the source and drain of each of the third and fourth column selection transistors, one of a source and drain of the eleventh column selection transistor being connected to the other of the source and drain of each of the fifth and sixth column selection transistors, one of a source and drain of the twelfth column selection transistor being connected to the other of the source and drain of each of the seventh and eighth column selection transistors; first and second sense amplifiers, the first sense amplifier being connected to the other of the source and drain of each of the ninth and tenth column selection transistors, and the second sense amplifier being connected to the other of the source and drain of each of the eleventh and twelfth column selection transistors; a first column selection line being connected to gates of the first, third, fifth and seventh column selection transistors; a second column selection line being connected to gates of the second, fourth, sixth and eighth column selection transistors; and third to sixth column lines being connected to gates of the ninth to twelfth column selection transistors, respectively.